DESCRIPTION
Designed for pulse width modulated (PWM) current control
of DC motors, the A3959 is capable of output curre nts to ±3 A
and operating voltages to 50 V. Internal fixed off-time PWM
current-control timing circuitry can be adjusted via control
inputs to operate in slow, fast, and mixed current-decay modes.
PHASE and ENABLE input terminals are provided for use
in controlling the speed a nd dir ection of a DC motor with
externally applied PWM-control signals. Internal synchronous
rectification c ontrol circuitry is pr ovided to re duce power
dissipation during PWM operation.
Internal circuit protection includes thermal shutdown w ith
hysteresis, undervoltage moni toring of su pply and charge
pump, and crossover-current protection. Special power-up
sequencing is not required.
The A3959 provides a choice of two power packages: a 24-lead
SOIC with four internally fused pins (package suffix ‘LB’),
and a thin (<1.2 mm) 28-pin TSSOP with an exposed thermal
pad (suffix ‘LP’). In all cases, the power pins and tabs are at
ground potential and need no electrical isolation. Each package
is lead (Pb) free, with 100% matte tin leadframes.
29319.37L, Rev. 14
MCO-0000727
FEATURES AND BENEFITS
±3 A, 50 V Output Rating
Low r
DS(on)
Outputs (270 m, Typical)
Mixed, Fast, and Slow Current-Decay Modes
Synchronous Rectification for Low Power Dissipation
Internal UVLO and Thermal-Shutdown Circuitry
Crossover-Current Protection
Internal Oscillator for Digital PWM Timing
DMOS Full-Brid ge PWM Motor Driver
PACKAGES:
Functional Block Diagram
Not to scale
A3959
Package LP, 28 -pin TSSOP
with exposed thermal pad
Package LB, 24-pin SOIC
with internally fused pins
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
BANDGAP
REGULATOR
V
DD
V
BB
+
LOGIC
SUPPLY
V
REG
CP1
CP
CP2
LOAD
SUPPLY
GATE DRIVE
Dwg. FP-048-2A
CONTROL LOGIC
SENSE
R
S
SLEEP
EXT MODE
PHASE
ENABLE
BLANK
PFD1
PFD2
REFERENCE
BUFFER &
÷10
CURRENT
SENSE
ZERO
CURRENT
DETECT
OUT
A
OUT
B
REF
PWM
TIMER
V
REF
C
S
OSC
ROSC
TO V
DD
TO V
DD
October 21, 2022
DMOS Full-Brid ge PWM Motor Driver
A3959
2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
SELECTION GUIDE
Part Number Package Packing
A3959SLBTR-T 24-pin SOIC with internally fused pins 1000 per reel
A3959SLPTR-T 28-pin TSSOP with exposed thermal pad 4000 per reel
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Notes Rating Units
Load Supply Volt age V
BB
50 V
Logic Supply Voltage V
DD
7.0 V
Input Voltage V
IN
Continuous –0.3 to V
DD
+ 0.3 V
t
w
< 30 ns –1.0 to V
DD
+ 1.0 V
Sense Voltage V
S
Continuous 0.5 V
t
w
< 3 µs 2.5 V
Reference Voltage V
REF
V
DD
V
Output Current I
OUT
Output current rating may be limite d by duty cycle, am-
bient temperature, and heat sinking. Under any set of
conditions, do not exceed the specied current rating
or a junction temperature of 150°C.
Repetitive ±3.0 A
Peak, < 3 µs ±6.0 A
Package Power Dissipation P
D
See Thermal Characteristics
Operating Ambient Temperature T
A
Range S –20 to 85 °C
Maximum Junction Tem perature T
J
(max)
Fault conditions that produce excessive junction temperature will activate
the de vice’s thermal shutdown circuitry. These conditions can be toler-
ated but should be avoided.
150 °C
Storage Temperature T
stg
–55 to 150 °C
DMOS Full-Brid ge PWM Motor Driver
A3959
3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
50 75 100 125 150
5
1
0
ALLOWABLE PACKAGE POWER DISSIPATION (W)
TEMPERATURE IN °°
°°
C
4
3
2
25
SUFFIX 'LP', R
θJA
= 40°C/W
SUFFIX 'LB', R
θJA
= 51°C/W
2-LAYER BOARD,
1 SQ. IN. COPPER EA. SIDE
SUFFIX 'LP', R
θJA
= 28°C/W
SUFFIX 'LB', R
θJA
= 35°C/W
4-LAYER BOARD
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions Value Units
Package Power Dissipation P
D
LB pa ckage 2.5 W
LP package 3.1 W
Package Thermal Resistance,
Junction to Ambient
R
θJA
LB Pa ckage
1-layer PCB, minimal exposed copper area 77 °C/W
2-layer PCB, 1-in.
2
2-oz copper exposed area 51 °C/W
4-layer PCB, based on JEDEC sta ndard 35 °C/W
LP Package
1-layer PCB, minimal exposed copper area 100 °C/W
2-layer PCB, 1-in.
2
2-oz copper exposed area 40 °C/W
4-layer PCB, based on JEDEC sta ndard 28 °C/W
Package Thermal Resistance,
Junction to Tab
R
θJT
LB pa ckage 6 °C/W
Package Thermal Resistance,
Junction to Pad
R
θJP
LP package 2 °C/W
*Additional thermal information available on Allegro website.
DMOS Full-Brid ge PWM Motor Driver
A3959
4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
Continued next page
Characteristics Symbol Test Conditions Min. Typ. Max. Units
OUTPUT DRIVERS
Load Supply Volt age Range V
BB
Operating 9.5 50 V
During sleep mod e 0 50 V
Output Leakage Current I
DSS
V
OUT
= V
BB
<1.0 20 µA
V
OUT
= 0 V <–1.0 –20 µA
Output On Resis tance r
DS(on)
Source driver, I
OUT
= –3 A 270 300 m
Sink driver, I
OUT
= 3 A 270 300 m
Crossover Delay 300 600 1000 ns
Body Diode Forw ard Voltage V
F
Source diode, I
F
= –3 A 1.6 V
Sink diode, I
F
= 3 A 1.6 V
Load Supply Current I
BB
f
PWM
< 50 kHz 4.0 7.0 mA
Charge pump on, outputs disabled 2.0 5.0 mA
Sleep mode 20 µA
CONTROL LOGIC
Logic Supply Voltage Range V
DD
Operating 4.5 5.0 5.5 V
Logic Input Voltage
V
IN(1)
2.0 V
V
IN(0)
0.8 V
Logic Input Current
(all inp uts except ENABLE)
I
IN(1)
V
IN
= 2.0 V <1.0 20 µA
I
IN(0)
V
IN
= 0.8 V <–2.0 –20 µA
Logic Supply Current I
DD
f
PWM
< 50 kHz 6.0 10 mA
Sleep mode 2.0 mA
ENABLE Input Current
I
IN(1)
V
IN
= 2.0 V 40 100 µA
I
IN(0)
V
IN
= 0.8 V 16 40 µA
Internal OSC Frequency f
OSC
R
OSC
shorted to GROUND 3.25 4.25 5.25 MHz
R
OSC
= 51 k 3.65 4.25 4.85 MHz
Reference Input Voltage Range V
REF
Operating 0.0 V
DD
V
Reference Input Current I
REF
V
REF
= V
DD
±1.0 µA
Comparator Input Offset Voltage V
IO
V
REF
= 0 V ±5.0 mV
ELECTRICAL CHARACTERISTICS at T
A
= +2C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (u nless noted otherwise)
DMOS Full-Brid ge PWM Motor Driver
A3959
5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
ELECTRICAL CHARACTERISTICS (continued) at T
A
= +2C, V
BB
= 50 V, V
DD
= 5.0 V, V
SENSE
= 0.5 V,
f
PWM
< 50 kHz (u nless noted otherwise)
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Reference Divider Ratio 10
Gm Error
(Note 3)
E
Gm
V
REF
= V
DD
±4.0 %
V
REF
= 0.5 V ±14 %
Propagation Delay Times t
pd
0.5 E
in
to 0.9 E
out
:
PWM change to source on 600 750 1200 ns
PWM change to source off 50 150 350 ns
PWM change to sink on 600 750 1200 ns
PWM change to sink off 50 100 150 ns
Thermal Shutdown Tem p. T
J
165 °C
Thermal Shutdown Hysteresis T
J
15 °C
UVLO Enable Threshold V
UVLO
Increasing V
DD
3.90 4.2 4.45 V
UVLO Hysteresis V
UVLO
0.05 0.10 V
NOTES: 1. Typical Data is for design information only.
2. Negative current is dened as coming out of (sourcing) the specied device terminal.
3. G
m
error = ([V
REF
/10] V
SENSE
)/(V
REF
/10) where V
SENSE
= I
TRIP
•R
S
.
DMOS Full-Brid ge PWM Motor Driver
A3959
6
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION
V
REG
. Th is internally generated voltage is used to operate
the sink-side DMOS outpu ts. The V
REG
terminal should
be decoup led with a 0.22 µF ca pacitor to ground. V
REG
is
internally monitored and in the case of a fault condition,
the outputs of the device are disabled.
Charge Pump. The charge pump is used to generate a
gate-supply voltage greater than V
BB
to drive the source-
side DMOS gates. A 0.22 µF ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes.
A 0.22 µF ceramic capacitor should be connected between
CP and V
BB
to act as a reservoir to operate the high-side
DMOS devices. The CP voltage is internally monitored
and, in the case of a fault condition, the source ou tputs of
the device are disable d.
PHASE Logic. The PHASE input terminal de termines if
the device is operating in the “forward” or “reverse” state.
PHASE OUT
A
OUT
B
0 Low High
1 High Low
ENABLE Logic. The ENABLE input terminal al lows
external PWM. ENABLE high turns on the selected sink-
source pair. ENABLE low switches o the source driver
or the source and sink driver, depending on EXT MODE,
and the load current decays. If ENABLE is kept high, the
current wi ll rise until it reaches the level set by th e internal
current-control circuit.
ENABLE Outputs
0 Chopped
1 On
EXT MODE Logic. When using external PWM current
control, the EXT MODE input determines the current path
during the chopped cy cle. With EXT MODE low, fast
decay mo de, the opposite pair of selected outputs will be
enabled during the o cycle. With EXT MODE high, slow
decay mo de, both sink drivers are on with ENABLE low.
EXT MODE Decay
0 Fast
1 Slow
Current Regulation. Load cu rrent is regulated by an
internal xed o-time PW M control circuit. When the
outputs of the DMOS H bridge are turned on, the current
increases in the motor winding un til it reaches a trip value
determined by the external sense resistor (R
S
) and the
applied analog reference voltage (V
REF
):
I
TRIP
= V
REF
/10R
S
At the trip point, the sense comparator resets the source-
enable lat ch, turning o the source driver. The load
inductance then causes the current to recirculate for the
xed o-time period. The curren t path during recirculation
is determined by the conguration of slow/mixed/fast
current-decay mode via PFD1 and PFD2.
Oscillator. The PWM timer is based on an int ernal
oscillator set by a resistor connected from the R
OSC
terminal to V
DD
. Typical value of 4 MHz is se t with a
51 k resistor. The allowable range of the resistor is from
20 k to 100 k.
f
OSC
= 204 x 10
9
/R
OSC
.
If R
OSC
is not pulled up to V
DD
, it must be shorted to
ground.
Fixed O Time. The A3959 is set for a xed o time of
96 cycles of the internal oscillato r, typically 24 µs with a
4 MHz oscillator.
DMOS Full-Brid ge PWM Motor Driver
A3959
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION (con tinued)
Internal Current-Control Mode. In puts PFD1 and
PFD2 determine the curre nt-decay method after an
overcurrent event is detected at the SENSE input. In slow-
decay mo de, both sink drivers are turned on for the xed
o-time period. Mixed-decay mode starts out in fast-decay
mode for a portion (15% or 48%) of the xed o time, and
then is followed by slow decay for the remainder of the
period.
PFD2 PFD1 % t
o
Decay
0 0 0 Slow
0 1 15 Mixed
1 0 48 Mixed
1 1 100 Fast
PWM Blank Timer. When a source driver turns on, a
current sp ike occurs du e to the reverse-recovery currents
of the clamp diodes and/or switching transients re lated to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable lat ch,
the sense comparator is blanked. The blank timer runs
after the o-time counter to provide the blanking function.
The blank timer is reset when ENABLE is chopped or
PHASE is changed. Fo r external PWM control, a PHASE
change or ENABLE on will trigger the blanki ng function.
The duration is determined by the BLANK input and the
oscilator.
BLANK t
blank
0 6/f
osc
1 12/f
osc
Synchronous Rectication. When a PWM o cycle
is triggered, either by an ENABLE chop command or
internal xed o-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A395 9 synchronous rectication featu re will turn on
the appropriate pair of DMOS outputs during the current
decay and eectively short out th e body diodes with the
low r
DS(on)
driver. This will reduce power dissipation
signicantly and can eliminate the need for external
Schottky diodes.
Synchronous rectication will prevent reversal of load
current by turning o all outputs when a zero-current level
is detecte d.
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on CP or V
REG
) the outputs of
the device are disable d until the fault condition is remove d.
At power up, and in the ev ent of low V
DD
, the UVLO
circuit dis ables the drivers .
Braking. The braking function is implemented by
driving th e device in slow-decay mode via EXTMODE
and apply ing an enable chop command. Because it is
possible to drive curre nt in either direction through the
DMOS drivers, this conguration eectively shorts out
the motor-generated BEMF as long as the ENABLE
chop mod e is asserted. It is important to note that the
internal PWM current-control circuit will not limit the
current when braking, because the current does not ow
through the sense resis tor. The maximum brake current
can be approximated by V
BEMF
/R
L
. Care should be taken
to ensure that the maximum ratin gs of the device are not
exceeded in worst-case braking situations of high speed
and high inertial loads.
SLEEP Logic. The SLEEP input terminal is used to
minimize power consumption when when not in use.
This disab les much of the internal circuitry includ ing the
regulator and charge pump. Logic low will put the device
into sleep mode, logic high will allow normal operation.
Note: If the sleep mode is not used, connect a 5 k pull-
up resistor between the SLEEP terminal and V
DD
.
DMOS Full-Brid ge PWM Motor Driver
A3959
8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION (con tinued)
Current Sensing. To minimize inaccuracies in
sensing th e I
TRIP
current le vel, which may be caused by
ground tra ce IR drops, the sense resistor should have an
independent ground return to the ground terminal of the
device. For low-value sense resistors the IR drops in the
PCB sense resistors traces can be signicant and should be
taken into account. The use of sockets should be avoided
as they can introduce variation in R
S
due to their contact
resistance.
The maximum value of R
S
is given as R
S
= 0.5/I
TRIP
.
Thermal Protection. Circuitry turns o al l drivers when
the junction temperature reaches 16C typically. It is
intended only to protect the device from failures due to
excessive junction temperatur es and should not imply that
output short circuits are permitted. Thermal shutdown has a
hysteresis of approximately 15°C.
Layout. A star ground system lo cated close to the driver
is recommended. The printed wiring board should use a
heavy gro und plane. For optimum electrical and thermal
performance, the driver should be soldered directly onto
the board. The ground side of R
S
should have an individual
path to the ground terminals of the device. This path should
be as short as is possible physically and should not have
any other components connected to it. It is recommended
that a 0.1 µF capacitor be placed between SE NSE and
ground as close to the device as possible; the load supply
terminal, V
BB
, should be decoupled with an electrolytic
capacitor (> 47 µF is recommended) placed as close to the
device as is possible. On the 28-lead TSSOP pack age, the
copper ground plane located under the exposed thermal pad
is typicall y used as a star ground.
DMOS Full-Brid ge PWM Motor Driver
A3959
9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
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PWM TIMER
V
BB
24
23
22
21
28
27
26
25
20
17
16
15
NC
SENSE
SLEEP
NO
CONNECTION
OUT
B
NC
LOAD SUPPLY
NC
OUT
A
NO
CONNECTION
EXT MODE
REF
V
REG
1
2
3
4
5
8
9
12
11
14
13
10
GROUND
GROUND
GROUND
CP
CP
2
CP
1
PHASE
NC
NC
V
DD
ENABLE
PFD
2
BLANK
PFD
1
LOGIC SUPPLY
θ
ROSC
LOGIC
NC
NC
CHARGE PUMP
÷
10
6
7
19
18
Terminal List
Package LB (SOI C)
PWM TIMER
V
BB
24
23
22
21
20
17
16
15
14
13
GROUND
GROUND
SLEEP
NO
CONNECTION
OUT
B
LOAD SUPPLY
SENSE
OUT
A
NO
CONNECTION
EXT MODE
REF
V
REG
Dwg. PP-069-4
1
2
3
4
5
8
9
12
11
10
GROUND
GROUND
CP
CP
2
CP
1
PHASE
V
DD
ENABLE
PFD
2
BLANK
PFD
1
LOGIC SUPPLY
θ
ROSC
LOGIC
NC
NC
CHARGE PUMP
÷
10
6
7
19
18
Package LP (TSS OP)
Terminal Name Terminal Description LB (S OIC) LP (TSSOP)
CP Reservoir capacitor (typically 0.22 µF) 1 1
CP1 & CP2 The charge pu mp capacitor (typically 0.22 µF) 2 & 3 2 & 3
NC No (in ternal) connection 4
PHASE Logic input for directio n control 4 5
ROSC Oscillator resistor 5 6
GROUND Grounds 6, 7 7, 8*
LOGIC SUPPLY VDD, the low voltage (ty pically 5 V) supply 8 9
ENABLE Logic input for enable control 9 10
NC No (in ternal) connection 11
PFD2 Logic-level input for fast decay 10 12
BLANK Logic-level input for blanking control 11 13
PFD1 Logic-level input for fast decay 12 14
REF VREF, the load current reference input voltage 13 15
EXT MODE Logic input for PWM mode control 14 16
NO CONNECT No (Internal) connection 15 17
OUTA One of two DMOS bridge outputs to the motor 16 18
NC No (in ternal) connection 19, 20
SENSE Sense resistor 17 21
NC No (in ternal) connection 22
GROUND Grounds 18, 19
LOAD SUPPLY VBB, the high-current, 9.5 V to 50 V, motor supply 20 23
OUTB One of two DMOS bridge outputs to the motor 21 24
NO CONNECT No (Internal) connection 22 25
SLEEP Logic-level Input for sleep operation 23 26
VREG Regulator decouplin g capacitor (typically 0.22 µF) 24 27
GROUND Ground 28*
* For the LP (TSSOP) package, the grounds at terminals 7, 8, and 28 should be connected together at th e exposed pad be-
neath the device.
DMOS Full-Brid ge PWM Motor Driver
A3959
10
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
LB package 24-pin SOICW
For Reference Only Not for Tooling Use
(Reference Allegro DWG-0000388, Rev. 1 and JEDEC MS-013AD)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold ash, gate burrs, and dambar protrusions
Exact case and lead conguration at supplier discretion within limits shown
Internal configuration of fused pins is device-dependent
C
GAUGE PLANE
SEATING PLANE
A
Terminal #1 mark area
C
21
24
Branding scale and appearance at supplier discretion
C
SEATING
PLANE
C0.10
2
0.25 BSC
2.64
2.44
15.40
15.20
10.51
10.11
0.30
0.10
0.32
0.23
1.01
0.51
A
1.27 BSC
0.46
0.36
Branded Face
7.60
7.40
R0.89
R0.63
B
2.20
0.65
9.60
1.27
PCB Layout Reference View
21
24
B
Reference pad layout (reference IPC SOIC127P1030X265-24M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
C
1
Standard Branding Reference View
XXXXXXXXX
Date Code
Lot Number
Line 1, 2, 3 = 15 Characters
Line 1: Part Number
Line 2: Logo A, 4 digit Date Code
Line 3: Assembly Lot Number
DMOS Full-Brid ge PWM Motor Driver
A3959
11
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
LP package 28-pin TSSOP
For Reference Only Not for Tooling Use
(Reference Allegro DWG-0000379, Rev. 3 and JEDEC MO-153AET)
Dimensions in millimeters NOT TO SCALE
Dimensions exclusive of mold ash, gate burrs, and dambar protrusions
Exact case and lead conguration at supplier discretion within limits shown
A
1.20 MAX
0.15
0.025
0.30
0.19
0.20
0.09
0.60 ±0.15
1.00 REF
C
SEATING
PLANE
C0.10
28X
0.65 BSC
0.25 BSC
21
28
9.70 ±0.10
4.40.10 6.40.20
GAUGE PLANE
SEATING PLANE
B
Branded Face
6.10
0.65
0.45
1.65
3.00
5.00
28
21
C
5.08 NOM
3 NOM
PCB Layout Reference View
A
B
C
Exposed thermal pad (bottom surface)
Terminal #1 mark area
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
Branding scale and appearance at supplier discretion.D
Standard Branding Reference View
Lines 1, 2, 3 = 10 characters
Line 1: Part Number
Line 2: Logo A, 4-digit Date Code
Line 3: Characters 5, 6, 7, 8 of
Assembly Lot Number
E
XXXXXXX
Date Code
Lot Number
DMOS Full-Brid ge PWM Motor Driver
A3959
12
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
For the latest version of this document, visit our website:
www.allegromicro.com
REVISION HISTORY
Number Date Description
13 November 1, 2019 Minor editorial updates
14 October 21, 2022 Removed discontinued B package option; updated package drawings (pages 10-11)
Copyright 2022, Allegro MicroSystems.
Allegro MicroSystems reserves the right to m ake, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or m anufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegros product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSys tems assumes no responsibility for its use; nor
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