
DMOS Full-Brid ge PWM Motor Driver
A3959
7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03 103-3353 U. S.A.
www.allegromicro.com
FUNCTIONAL DESCRIPTION (con tinued)
Internal Current-Control Mode. In puts PFD1 and
PFD2 determine the curre nt-decay method after an
overcurrent event is detected at the SENSE input. In slow-
decay mo de, both sink drivers are turned on for the xed
o-time period. Mixed-decay mode starts out in fast-decay
mode for a portion (15% or 48%) of the xed o time, and
then is followed by slow decay for the remainder of the
period.
PFD2 PFD1 % t
o
Decay
0 0 0 Slow
0 1 15 Mixed
1 0 48 Mixed
1 1 100 Fast
PWM Blank Timer. When a source driver turns on, a
current sp ike occurs du e to the reverse-recovery currents
of the clamp diodes and/or switching transients re lated to
distributed capacitance in the load. To prevent this current
spike from erroneously resetting the source-enable lat ch,
the sense comparator is blanked. The blank timer runs
after the o-time counter to provide the blanking function.
The blank timer is reset when ENABLE is chopped or
PHASE is changed. Fo r external PWM control, a PHASE
change or ENABLE on will trigger the blanki ng function.
The duration is determined by the BLANK input and the
oscilator.
BLANK t
blank
0 6/f
osc
1 12/f
osc
Synchronous Rectication. When a PWM o cycle
is triggered, either by an ENABLE chop command or
internal xed o-time cycle, load current will recirculate
according to the decay mode selected by the control logic.
The A395 9 synchronous rectication featu re will turn on
the appropriate pair of DMOS outputs during the current
decay and eectively short out th e body diodes with the
low r
DS(on)
driver. This will reduce power dissipation
signicantly and can eliminate the need for external
Schottky diodes.
Synchronous rectication will prevent reversal of load
current by turning o all outputs when a zero-current level
is detecte d.
Shutdown. In the event of a fault (excessive junction
temperature, or low voltage on CP or V
REG
) the outputs of
the device are disable d until the fault condition is remove d.
At power up, and in the ev ent of low V
DD
, the UVLO
circuit dis ables the drivers .
Braking. The braking function is implemented by
driving th e device in slow-decay mode via EXTMODE
and apply ing an enable chop command. Because it is
possible to drive curre nt in either direction through the
DMOS drivers, this conguration eectively shorts out
the motor-generated BEMF as long as the ENABLE
chop mod e is asserted. It is important to note that the
internal PWM current-control circuit will not limit the
current when braking, because the current does not ow
through the sense resis tor. The maximum brake current
can be approximated by V
BEMF
/R
L
. Care should be taken
to ensure that the maximum ratin gs of the device are not
exceeded in worst-case braking situations of high speed
and high inertial loads.
SLEEP Logic. The SLEEP input terminal is used to
minimize power consumption when when not in use.
This disab les much of the internal circuitry includ ing the
regulator and charge pump. Logic low will put the device
into sleep mode, logic high will allow normal operation.
Note: If the sleep mode is not used, connect a 5 kΩ pull-
up resistor between the SLEEP terminal and V
DD
.